Course : VLSI Design and Veriflication with Verilog HDL - Download PDF
Duration : 3 days (5-6hrs/day)
Dates : As per mutual agreement
Time : 5 Hr/Day (Minimum)
Eligibility : BE/BTech/ME/MTech (CSE / E&TC / Electronics) Thrid, Final year students.
Key Objectives :
1. Learn basic semiconductor theory, IC fabrication flow and logic
design with CMOS.
2. Review of digital electronics concepts, IC design flow, Learn Verilog language.
3. Learn Modeling, Design, Verification concepts.
Results
: At the end of training session you will be able to write your own
Design and Verification environment in Verilog, Verilog is
2. Review of digital electronics concepts, IC design flow, Learn Verilog language.
3. Learn Modeling, Design, Verification concepts.
commonly used in most of the IC design industry compared with other HDL like VHDL. Students will get benefit of early
knowledge before going to Industry.
Skills developed :
1. basic semiconductor theory, IC
fabrication flow and logic design with CMOS, IC
design flow
2. Design and Verification knowledge
3. Verilog as language
2. Design and Verification knowledge
3. Verilog as language
Quick review of Digital Electronics Basic Semiconductor Theory Fabrication process – CMOS CMOS Transistors basics Digital Logic Experiment : Design circuit using CMOS Boolean algebra Sequential and combinational logic IC design flow introduction Verilog language detail study What is HDL? What is LRM Verilog HDL design flow. HDL modelling techniques Verilog History and lexical conventions Simulation and synthesis ? Verilog modelling structure Verilog models, Verification structure Specification, top level view of DUT and TB LAB 1: How to interpret SPECIFICATION Lexical Conventions Language essential (White space, identifiers, number, System task and function, compiler directive) LAB 2 : `timescale Basic code structure Module, port, instantiation Parameterise modules. 2001 and 95 style of module declaration. LAB 3 : Module declaration Verilog data types Net and Variable Resolution type Multidimensional arrays LAB 4 : 2D array memory model Procedural assignment and statements Procedural block overview initial block always block and sensitivity list assign statement Delay timing control How simulator works. Event Queue and Delta Procedural block and synthesis issues. Blocking and non-blocking assignments with event queue Modelling delays in HDL ( inertial and transport) LAB 5 : and gate with inertial delay LAB 6 : and gate with transport delay Procedural statement If..else, case, forever, repeat, while, disable and synthesis issues. LAB 7: 8 bit adder design and synthesis How to write combinational logic with always block and synthesis issues. LAB8 - Design MUX using always with continuous assignment LAB9 - Design MUX using assign Verilog gate level primitive. Function and task in combinational logic. Zero delay loops Latches in synthesis LAB10 - Experience latches Example of async. Adder and subtracter |
How to write sequential logic Types of sequential logic Basic DFF design with synchronous reset. DFF with a-synchronous reset. LAB 11 : DFF with synchronous reset LAB 12 : DFF with asynchronous reset Level sensitive models Shift registers and synthesis with blocking and non-blocking assignments. Example of synchronous adder and subtracter LAB 13 : 8 bit counter design Procedural calls : task and function User defines calls User define function, scope and synthesis issues. LAB 14 : 7 segment display User define task Task and testbench example of adder. Simulation timings Type of delays, flop-flop, combinational, interconnect delays. Timings at RTL modeling. Timings after synthesis Cell library design and specify block Netlist and SDF Post layout timings LAB 15 : Counter synthesis and SDF annotation Bi-directional and tri-state buffers tri in verilog SoC interconnecting bus architecture. tri-state implementation with simple bus example tri-state with assign statement. tri-state with always block LAB 16 : Memory design with inout data bus How to write FSM FSM types Mealy and Moore machine. Example of sequence detection circuit Design state machine. Write FSM (Sequential and combinational block of state mechine) Writing one-hot example of FSM LAB 16: Sequence detector FSM design How to write test benches What is TB Verification flow review. Advance verification architecture Step by step sequence detector testbench TB clock generation. TB reset generation. TB data generation and dummy model. TB comparator or scoreboard. Compiler directives used in TB Memory initialization used in TB $monitor and $strobe used in TB force release used in TB File IO in TB LAB 17 – Write TB for FIFO CPLD and FPGA Target technology Why programmable logic is required programmable logic fundamental understanding PAL, CPLD, FPGA architecture Spartan3an architecture overview Examples to use Sparten3an FPGA board. LAB 18 – LED, LCD, Keyboard or switch control. Etc. |
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